1. Field of the Invention
The present invention relates to a liquid crystal display device which includes a plurality of liquid crystal pixels arrayed substantially in a matrix and drives the liquid crystal pixels of each row in at least two steps, and more particularly to a liquid crystal display device in which liquid crystal driving voltages for the liquid crystal pixels are set at opposite polarities in every predetermined number of rows.
2. Description of the Related Art
Liquid crystal display devices have widely been used to display images in computers, car navigation systems or TV receivers.
A liquid crystal display device, in general, includes a liquid crystal display panel having a structure that a liquid crystal layer is held between an array substrate and a counter-substrate. In an active-matrix liquid crystal display panel, an array substrate includes a plurality of pixel electrodes which are arrayed substantially in a matrix, a plurality of scanning lines which are disposed along the rows of pixel electrodes, a plurality of signal lines which are disposed along the columns of pixel electrodes, and a plurality of pixel switching elements which are disposed near intersections between the scanning lines and signal lines. The scanning lines are sequentially driven by a scanning line driver disposed adjacent to one ends of the scanning lines. The signal lines are driven by a signal line driver disposed adjacent to one ends of the signal lines, while each scanning line is being driven. Each of the pixel switching elements is composed of, e.g. a thin-film transistor, and turned on to apply the potential of the associated signal line to the associated pixel electrode when the associated scanning line is driven. On the counter-substrate, a common electrode is provided so as to face the pixel electrodes. A pair of the pixel electrode and the common electrode serves as a liquid crystal pixel in associated with a pixel region that is part of the liquid crystal layer between the pixel electrode and the common electrode. In each liquid crystal pixel, the alignment of liquid crystal molecules in the pixel region is controlled by an electric field corresponding to a liquid crystal driving voltage that is a potential difference between the pixel electrode and the common electrode.
In the conventional art, there has been proposed a technique of driving liquid crystal pixels of each row in two steps, thereby to reduce the circuit scale of a signal line driver (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 2003-295834). In this technique, for example, as shown in FIG. 9, analog switches ASW1, ASW2, ASW3, ASW4, . . . , are provided as a multiplexer between output buffers D1, D2, . . . , of the signal line driver and signal lines X1, X2, X3, X4 . . . . The analog switches ASW1, ASW4, . . . , are controlled by a control signal CTL0, and the analog switches ASW2, ASW3, . . . , are controlled by a control signal CTL1. Transitions of the control signal CTL0 and control signal CTL1 are shown in FIG. 10.
The analog switches ASW1 and ASW4 are simultaneously turned on upon a fall of the control signal CTL0, so as to electrically connect the output buffers D1 and D2 of the signal line driver to the signal lines X1 and X4. The analog switches ASW2 and ASW3 are simultaneously turned on upon a fall of the control signal CTL1, so as to electrically connect the output buffers D1 and D2 of the signal line driver to the signal lines X3 and X2. Specifically, if the transitions of the control signals CTL0 and CTL1 are determined to alternately turn on the analog switches ASW1 and ASW4 and the analog switches ASW2 and ASW3 during the period in which each of the scanning lines Y1, Y2, Y3, Y4, . . . , is driven, the liquid crystal pixels PX of the associated row are driven in two steps. In this structure, the necessary number of output buffers D1, D2, . . . , of the signal line driving circuit is only half the number of signal lines X1, X2, X3, X4, . . . . Therefore, the circuit scale of the signal line driver can be reduced. The actual signal line driver is composed of driver ICs each having a predetermined number of output buffers. As a result, the number of driver ICs is reduced. In FIG. 9, the signal lines X2 and X3 are connected to the analog switches ASW3 and ASW2 in a crossed fashion. This structure is effective in the case where the liquid crystal driving voltages to the liquid crystal pixels PX of each row, that is the potentials of pixel electrodes PE relative to the potential of the common electrode CE are set at opposite polarities on a column-by-column basis. In other words, relative to the polarities of pixel voltages Vs which are output from the output buffers D1 and D2 in a first driving step, there is no need to invert the polarities of pixel voltages Vs which are output in a second driving step. Therefore, the power consumption of the signal line driver and the charging error can be reduced.
As a measure for preventing fluctuations in brightness, which is called “flicker”, pixel voltages are set at opposite polarities on a row-by-row basis, for example. In particular, there is a problem that the flicker becomes conspicuous at a time of displaying a checkered crosshatch-dot pattern. To solve this problem, it is preferable to set the pixel voltages at opposite polarities in units of a predetermined number of at least two pixel rows. In the case where the predetermined number of pixel rows are four pixel rows, as show in FIG. 9, the potential polarities of the signal lines X1 to X4 transition in every four horizontal scanning periods (4H), as shown in FIG. 10.
However, this polarity control may cause unwanted potential variation in the signal lines X1, X4, . . . . In the case where the control signals CTL0 and CTL1 transition in the first half and second half of each horizontal scanning period, as shown in FIG. 10, the signal lines X1 and X4 are connected to the output buffers D1 and D2 of the signal line driver while the signal lines X2 and X3 are in the floating state, and the signal lines X2 and X3 are connected to the output buffers D2 and D1 of the signal line driver while the signal lines X1 and X4 are in the floating state. Each pixel electrode PE retains the potential that is set via an associated pixel switching element T. Subsequently, as shown in FIG. 9, a parasitic capacitance Csd-R and a parasitic capacitance Gsd-L appears between the pixel electrode PE and the right-hand neighboring signal line X and between the pixel electrode PE and the left-hand neighboring signal line X. In this case, when the control signal CTL1, as encircled in FIG. 10, falls in the second half of the 1 horizontal scanning period for a pixel line L1, which is the first one of four rows of liquid crystal pixels PX, the potential of the signal line X2 transitions from the positive polarity to the negative polarity due to the polarity inversion of the pixel voltage Vs that is output from the output buffer D2, and the potential of the signal line X3 transitions from the negative polarity to the positive polarity due to the polarity inversion of the pixel voltage Vs that is output from the output buffer D1. At this time, the potential of the signal line X1 is affected by the potential variation of the signal line X2 due to the presence of a capacitance-coupled path which extends from the signal line X2 to the signal line X1 via the parasitic capacitance Csd-R, the pixel electrode PE in the potential-retention state and the parasitic capacitance Csd-L. In addition, the potential of the signal line X4 is affected by the potential variation of the signal line X3 due to the presence of a capacitance-coupled path which extends from the signal line X3 to the signal line X4 via the parasitic capacitance Csd-L, the pixel electrode PE in the potential-retention state and the parasitic capacitance Csd-R. Specifically, variation occurs in the potentials of the pixel electrodes PE which are connected to the signal lines X1 and X4 via pixel switching elements T in the pixel line L1. The potentials that have varied are retained in the pixel electrodes PE when all the pixel switching elements T for the pixel line L1 are simultaneously turned off. As a result, as shown in FIG. 11, horizontal stripes with two-dot intervals occur in every four pixel rows on the display screen. In this case, the gradations of all pixels are set at equal levels in order to make it easier to observe horizontal stripes. Such horizontal stripes occur not only in the case where pixel voltages Vs are set at opposite polarities in every four pixel rows, but also in the case where pixel voltages Vs are set at opposite polarities, for example, in every two pixel rows or every three pixel rows.